1. Field of the Invention
The invention relates to the design of a Gray code counter and more particularly to a Gray code counter using a series of identical Gray code cells.
2. Description of the Related Art
Gray code counters counting up or down are know to be difficult to design. This is particularly true of Gray code counters with many stages (bits). One way to get around this problem is to convert a Gray code counter to a binary counter, do the incrementing or decrementing in binary and reconvert to a Gray code counter. This method is very inefficient, taking a lot of extra logic and thus chip area and power. A related art paper, Reference 1, is “Clock-Gating and Its Application to Low Power Design of Sequential Circuits” by Qing W U, Massoud PEDRAM, and Xunwei W U, Proc. of the IEEE Custom Integrated Circuits Conference, 2000.
A previous paper by the inventor of the present invention, Reference 2, “Gray counters implementation for direct increment/decrement”, Nir Dahan, Sep. 10, 2006, prior art database reference IPCOM 000138896D.
However, there is a great pressure to further reduce the chip area and power consumption and to provide an efficient way for clock division which calls for new approaches not found in the related art and which the present invention addresses. Using a Gray structure/counter for clock division has the benefit that each of the different divisions (with the exception of the division by 2 stage) is changing on a different clock edge. This in turn helps tackle issues in complex chips such as IR drop by avoiding that a lot of current is pulled from the supply at once.
U.S. Patents and papers that relate to the present invention are:
U.S. Pat. No. 7,194,500 (Clift) describes a modular Gray code counter where each module comprises a flip-flop and a number of logic blocks. The first and last stage are given special consideration. Each module has five inputs and a clock input and two outputs the latter generally feeding the next stage.
U.S. Pat. No. 6,636,525 (Weng) discloses a modular Gray code counter capable of counting any number of elements. Each module, comprising a flip-flop and two or three logic blocks, has two inputs in addition to a clock and reset and two outputs. The two inputs of the flip-flop are fed by the outputs of the previous flip-flop.
U.S. Pat. No. 6,269,138 (Hansson) shows a low power Gray code counter which compares favourably to a low power binary counter. The counters consume a minimum of power when they are disabled and activated only when the data output has to be changed. Gray code stages comprise two flip-flops and typically three logic blocks.
“Gray counters in VHDL”, by Ing. Ivo Viscor, In “Proceedings of the Student FEI 2000, Brno 2000, pp. 399-401, discusses the use of Very High Speed Integrated Circuit (VHSIC) Hardware Description Language (VHDL) for designing a Gray code counter. Requirements were code simplicity and adjustable width of the counter, auxiliary bit generation, a series of one-bit blocks and glue logic for MSB generation.
It should be noted that none of the above-cited examples of the related art provide the advantages of the below-described invention.